Engineering and Logical Problem Set

Problem Statement

Question 1: Routing Grid Analysis Refer to the adjoining routing grid figure. A chip's routing region is represented as a 5-row × 6-column grid of routing tiles. Each tile displays its routing cost (combining wire delay and congestion penalty). The source pin is located in tile Row 1, Column 1 (marked 'S' on the grid) and the sink pin is located in tile Row 5, Column 6 (marked 'T' on the grid). Movement is restricted to rightward (same row, next column) or downward (same column, next row) only. The total routing cost of a path equals the sum of the routing costs of all tiles traversed, including the source and sink tiles. The route is laid on two metal layers: rightward moves use Metal-3 (M3), and downward moves use Metal-4 (M4). The route begins on the layer corresponding to its first move direction. A via is inserted at each point where the route changes direction (rightward-to-downward or downward-to-rightward). Wire resistance per rightward move = 2 Ω. Wire resistance p