Company: test1
Difficulty: medium
An FPGA-based digital system is programmed to decode a 7-bit instruction using a PLA-based decoder. During runtime, some instructions produce incorrect outputs only for specific address lines. What is the likely design issue? The decoder is implemented using ROM logic. The OR array in the PLA is floating. The AND array terms are not fully covered. Instruction timing constraints are violated. A communication system operates with 10 W of transmit power over a 1 MHz channel. The noise power spectral density is N0 = 10^-9 W/Hz. What is the channel capacity in Mbps? 6.02 Mbps 9.97 Mbps 13.29 Mbps 8.12 Mbps A broadcasting station uses amplitude modulation to transmit signals. The carrier amplitude is 100 V, and the modulation index is 0.8. The antenna connected to the transmitter has an effective resistance of 50 ohms. To ensure signal clarity without distortion, what percentage of the total transmitted power should lie in the sidebands? 0.4826 0.2424 0.2056 0.5234 Which microprocessor signa