Microsoft

The recruitment process consisted of two rounds: an Online Assessment and an Interview. Both of these evaluation stages were conducted online (virtually). Round 1 (Online Assessment): This initial phase had three parts, with a total duration of 120 minutes. Here's what each part included: Cognitive Test (30 minutes): This part had 20 questions related to Data Interpretation and Reasoning. The questions covered topics like recognizing patterns, solving series of numbers, working with time, distance, directions, profit, loss, probability, and permutations. Analog Electronics (45 minutes): The second part included 20 questions, mostly about RLC circuits, Operational Amplifiers, network theorems, circuit theory, and some questions related to control systems. Digital Electronics (45 minutes): In the third part, there were 20 questions covering various topics, including ANSI-C, Pipelining, Latches, flip-flops, 8085 programming, memory, and logical circuits. For each part, you got +1 for correct answers but -0.25 for incorrect ones. After the Online Assessment, 14 candidates were selected for Analog interviews, and 7 were selected for digital interviews. Two candidates, including me, were shortlisted for both Analog and Digital interviews. Round 2 (Technical Interview): Here, I will discuss my Digital Interview. The interview lasted for about 60-65 minutes (on Cisco Webex). Here are some questions asked in the interview:-  Could you please introduce yourself?  You mentioned your involvement in a radar-related project. Could you provide more details about it?  What exactly was the work you did there? (Here, I explained in detail about the project. It is related to Firmware development and Digital Design of a Radar Controller)  Subsequently, most of the interview questions revolved around my project: o I was asked about Interfacing, including SPI and UART. o How did you go about detecting incoming patterns? (Indirectly, they were asking to design a pattern detector.)o Explain the logic behind the firmware. (How data was stored, peripherals used, signal flow etc.) o How did you determine when data was transferred to the FPGA? (Pattern detector was employed for this purpose.) o Some more questions related to the project.  Following the project discussion, I was asked about setup and hold time, measures to prevent setup and hold violations, the concept of a metastable state, and the impact of changes in clock frequency on setup and hold time, etc.  Lastly, I was asked to design an even-odd parity checker. Later that night, we received notifications about the selected candidates. One student was chosen for the Analog Engineer role, one for the Digital Engineer role (I got selected for this role), and three for the Software Development Engineer role.