UPscale AI

Written Test (1 hour) The written exam was conducted on paper and mainly covered aptitude and digital electronics. The technical portion included topics such as: Finite State Machines (FSMs) Frequency divider design Full adder logic One C++ programming question A simple Verilog/SystemVerilog question where the task was to identify mistakes in the given code For aptitude practice, platforms like Indiabix and GeeksforGeeks were helpful. The test was supervised by the Upscale AI team. Interview – Round 1 (In Office) What is UART? Packet Parsing Block Design You are given a module that receives data one byte per cycle. Each packet contains: 1-byte header (read/write indicator) 4-byte address Data bytes (payload) The logic must separate these fields and route them to different buses: If the header indicates a write, send the data bytes to the data bus at the given address. If the header indicates a read, initiate a read at the address and forward the returned data to the address bus. The task is to design this module in Verilog. Duty-Cycle Modification Block Design logic that takes an input clock and outputs a new clock signal where the duty cycle is ~66.66% — meaning: Output stays HIGH for 2 input cycles, Then LOW for 1 cycle, repeating continuously. Interview – Round 2 (In Office) Sliding-Window Bit Counter A continuous bit stream arrives (1 bit each cycle). The block must output the number of 1’s seen in the last 20 cycles. When scaling this window from 20 → 100 cycles or more, what challenges arise, and what solutions exist? (e.g., shift registers getting large, timing issues, power increase, etc.) STA Question — Fixing Setup Violations If a timing path has a setup violation, what methods can you apply to fix it without introducing new setup or hold violations elsewhere? (Backend-focused question.) Tools Experience What tools have you used in the RTL-to-GDS flow?