Marvell Technology

Role: PD Intern (Physical Design Intern)

College: Not Specified

Interview Date: Not Specified (Post date October 1, 2025, but provides relevant advice for recent interviews)

Interview Type: Internship

Result: Not Specified

Difficulty: Hard (Implied by advanced technical topics)

Rounds: Not Specified (Advice focuses on technical topics rather than round structure)

Topics Asked: Static Timing Analysis (STA) fundamentals (setup/hold time, clock skew, clock-to-Q delay, constraints, timing paths, violations), TCL scripting, Python for basic automation, full Physical Design (PD) flow (STA fit, timing closure with place and route), MOSFET basics (delay variation with PVT corners, wire parasitics)

Experience:

This experience provides advice for a Marvell PD intern interview, detailing key areas to focus on.

Candidates should "nail the timing fundamentals," including setup and hold time, clock skew, clock-to-Q delay, and how constraints are established. Interviewers are likely to ask candidates to walk through timing paths and explain violations.

Proficiency in scripting is crucial, particularly TCL for daily use with tools like PrimeTime or Tempus, and Python for basic automation tasks.

A good understanding of the full Physical Design (PD) flow is expected, specifically knowing where Static Timing Analysis (STA) fits in and how timing closure works iteratively with place and route.

Knowledge of MOSFET basics, such as how delay varies with PVT (Process, Voltage, Temperature) corners and how wire parasitics affect timing, is also considered fair game, demonstrating an understanding of the underlying hardware.

For an internship, the focus is on demonstrating the ability to learn and having a strong foundation rather than being an expert. Being able to coherently explain a timing path, write a simple TCL script to parse a timing report, and discuss why fast corners are important for hold and slow corners for setup will be beneficial.